DM9102H

Integrated Fast Ethernet MAC, Physical Layer and Transceiver in one chip

128 pin LQFP with CMOS process

+1.8/3.3V Power supply with +5V tolerant I/O

Comply with PCI specification 2.2

PCI clock up to 66MHz

PCI bus master architecture

PCI bus burst mode data transfer

Two large independent transmission and receipt of FIFO

Support transmit threshold under-run re-try mode

Up to 256K bytes Boot EPROM or Flash interface

EEPROM 93C46 interface automatically supports node ID load and configuration information

Comply with IEEE 802.3u 100Base-TX and 802.3 10Base-T

Comply with IEEE 802.3u auto-negotiation protocol for automatic link type selection

Support IEEE 802.3x Full Duplex Flow Control

VLAN frame length support

IP/TCP/UDP checksum generation and checking

Comply with ACPI and PCI Bus Power Management

Support the MII (Media Independent Interface) for an external PHY

Support Wake-On-LAN function and remote wake-up

Support 4 Wake-On-LAN (WOL) signals

Lan Transformer  100Base-TX and 10Base-TX   YT18-2601S or 16YM001 or YL2J212A

High performance 100Mbps clock generator and data recovery circuit

Digital clock recovery circuit, using advanced digital algorithm to reduce jitter

Provides Loop-back mode for easy system diagnostics

Support auto-MDIX